Wafer Level Package By Using Post Dicing Process

• doi: 10.1109/ICEP.2014.6826656
• title: Wafer level package by using post dicing process
• publisher: IEEE
• isbn: 978-4-904090-10-7
• issn:
• rank: 3989
• access_type: LOCKED
• content_type: Conferences
• abstract: This paper describes the new wafer level packaging process with the diced chip array on the small-diameter handling wafer. The general purpose of wafer level packaging is to realize a smaller, more functional and cost effective electronic package. For example, Wafer Level chip size package and Wafer stacking 3D package are the most effective packaging processes/structures using semiconductor wafer process. In the semiconductor industrial trend, silicon wafer sizes become larger to achieve a higher chip throughput and to reduce a chip cost. However in actual applications, the packaging needs are diversified and the required number of each package type does not meet the huge sized wafer processing. In this paper, we introduce the new packaging technique. In this new technique, after dicing CMOS wafer to the individual chips, we rearrange them on another smaller handling wafer. We, then, planarize the surface after filling up the resin on it, which can be used just like a single wafer. As the result, we can have a free hand to choose the size of handling wafer, and it means that we can use the existing equipment, which leads to lower cost and shorter development time. First, the influence of residual stress after rearranging the matrix of chip on the handling wafer was investigated with using FEM-modeling. It was found that the both of the sell size of the matrix and the material properties of the filled resin greatly influence on the wafer warpage, and that the design of matrix and the material of resin are key to complete the process of this new technique. Second, we tried to apply this new technique to an image sensor. 8×8 matrix of 9mm2 CMOS image sensor chips are rearranged on 4inch glass wafer, and we fabricated TSVs in the image sensor chips for chip size package.
• article_number: 6826656
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6826656
• html_url: https://ieeexplore.ieee.org/document/6826656/
• abstract_url: https://ieeexplore.ieee.org/document/6826656/
• publication_title: 2014 International Conference on Electronics Packaging (ICEP)
• conference_location: Toyama, Japan
• conference_dates: 23-25 April 2014
• publication_number: 6821728
• is_number: 6826643
• publication_year: 2014
• publication_date: 23-25 April 2014
• start_page: 34
• end_page: 38
• citing_paper_count: 2
• citing_patent_count: 0
• download_count: 425
• insert_date: 20140609
• index_terms:
  • ieee_terms:
    • Bonding
    • Resins
    • Glass
    • Image sensors
    • Accuracy
    • Semiconductor device modeling
  • author_terms:
    • 3D package
    • WL-CSP
    • TSV
    • CMOS image sensor
  • dynamic_index_terms:
    • Wafer Level
    • Wafer-level Packaging
    • Image Sensor
    • Camera Sensor
    • Array Chip
    • Chip Size
    • Glass Wafer
    • Individual Chips
    • Electrode
    • Medical Devices
    • Medical Providers
    • Medical Supplies
    • Medical Equipment
    • Localization Accuracy
    • Positioning Accuracy
    • Finite Element Method
    • Process Flow
    • Photolithography
    • Optical Lithography
    • Small Packages
    • Alignment Marks
    • Flip-chip
    • Microbumps
    • Camera Module
    • UV-curable Resin
• isbn_formats:
  • format: CD, value: 978-4-904090-10-7, isbnType: New-2005
  • format: Electronic ISBN, value: 978-4-904090-11-4, isbnType: New-2005
• authors:
  • Author Name: Noriyuki Fujimori
    Affiliation: JISSO Technology Department, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37085405163
    ID: 37085405163
    Order: 1
    Author Affiliations:
    • JISSO Technology Department, Nagano, Japan
  • Author Name: Takatoshi Igarashi
    Affiliation: JISSO Technology Department, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086386652
    ID: 37086386652
    Order: 2
    Author Affiliations:
    • JISSO Technology Department, Nagano, Japan
  • Author Name: Takahiro Shimohata
    Affiliation: JISSO Technology Department, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086731830
    ID: 37086731830
    Order: 3
    Author Affiliations:
    • JISSO Technology Department, Nagano, Japan
  • Author Name: Takuro Suyama
    Affiliation: JISSO Technology Department, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086175340
    ID: 37086175340
    Order: 4
    Author Affiliations:
    • JISSO Technology Department, Nagano, Japan
  • Author Name: Kazuhiro Yoshida
    Affiliation: JISSO Technology Department, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086734161
    ID: 37086734161
    Order: 5
    Author Affiliations:
    • JISSO Technology Department, Nagano, Japan
  • Author Name: Yusuke Nakagawa
    Affiliation: JISSO Technology Department, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37089109453
    ID: 37089109453
    Order: 6
    Author Affiliations:
    • JISSO Technology Department, Nagano, Japan
  • Author Name: Tsutomu Nakamura
    Affiliation: JISSO Technology Department, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37085404540
    ID: 37085404540
    Order: 7
    Author Affiliations:
    • JISSO Technology Department, Nagano, Japan
  • Author Name: Toshiro Sato
    Affiliation: Interdisciplinary Graduate School of Science and Technology, Shinshu University, Nagano, Japan
    Author URL: https://ieeexplore.ieee.org/author/37309776400
    ID: 37309776400
    Order: 8
    Author Affiliations:
    • Interdisciplinary Graduate School of Science and Technology, Shinshu University, Nagano, Japan

Image Sensor

• sensor_type: CMOS
• resolution: Not specified
• dynamic_range: Not specified
• pixel_size: Not specified
• dark_current: Not specified

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

Applications & Benefits

• cell_imaging: The paper indicates application in medical devices such as camera modules of smart-phones and medical capsule endoscopes, contributing to the size reduction and minimal invasiveness of medical devices.
• benefits: Achieves smaller, functional and cost-effective electronic packages.

Supporting Organizations

• supported_by: Olympus Corporation, Shinshu University

Manuscript Details

• publication_date: 23-25 April 2014

Relevancy Score

• score: 10
• missing_fields:
  • resolution
  • dynamic_range
  • pixel_size
  • dark_current
  • focal_length
  • aperture
  • field_of_view
  • distortion
  • frame_rate
  • signal_to_noise_ratio
  • sensitivity
  • shutter_speed
  • power_consumption
  • noise

Processed JSON Filename

request_1cf8f9d6-b10c-420b-b4c3-ab88e6736ed4-wafer_level_package_by_using_post_dicing_process.json