Through Silicon Via And 3D Waferchip Stacking Technology

• doi: 10.1109/VLSIC.2006.1705326
• title: Through Silicon Via and 3-D Wafer/Chip Stacking Technology
• publisher: IEEE
• isbn: 1-4244-0006-6
• issn: 2158-5636
• rank: 3848
• access_type: LOCKED
• content_type: Conferences
• abstract: Through silicon via and 3D wafer/chip stacking technology is thought to be the essential technology of the next generation high-end semiconductors such as high-speed microprocessors and high-speed memories. However, there are many issues regarding LSI design, process integration, thermal management, and cost are under development. Cost is one of the most critical issues to apply this technology to products. We propose to categorize the through via application into three areas, i.e. low-end, middle range and high-end. High-end area that covers fast MPUs and fast memories need very small through vias to realize high-speed signal transmission between devices. Low-end area that covers image sensors, stacked memories and discrete does not always need high-speed signal transmission, but they need ultimate low cost. Thus, we developed novel through via fabrication technology employing printed circuit board (PCB) fabrication processes. The technology was applied to a CMOS image sensor wafer and successfully demonstrated
• article_number: 1705326
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1705326
• html_url: https://ieeexplore.ieee.org/document/1705326/
• abstract_url: https://ieeexplore.ieee.org/document/1705326/
• publication_title: 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.
• conference_location: Honolulu, HI, USA
• conference_dates: 15-17 June 2006
• publication_number: 11174
• is_number: 35987
• publication_year: 2006
• publication_date: 15-17 June 2006
• start_page: 89
• end_page: 92
• citing_paper_count: 56
• citing_patent_count: 46
• download_count: 2527
• insert_date: 20070220
• index_terms:
  • ieee_terms:
    • Silicon
    • Stacking
    • Costs
    • Thermal management
    • Fabrication
    • CMOS technology
    • Microprocessors
    • Large scale integration
    • Process design
    • Image sensors
  • dynamic_index_terms:
    • Through Silicon Via
    • Stacking Technology
    • Silicon Vias
    • Low Cost
    • Fabrication Process
    • Image Sensor
    • Camera Sensor
    • Printed Circuit Board
    • High-speed Transmission
    • Raman Spectroscopy
    • Raman Spectra
    • Chemical Vapor Deposition
    • Vapor Deposition
    • Chemical Deposition
    • Laser Ablation
    • Photoaging
    • Silicon Wafer
    • Transmission Electron Microscopy Observations
    • Electroplating
    • Electrochemical Deposition
    • Sensor Fabrication
    • Sensor Material
    • Textile Sensors
    • Reactive Ion Etching
    • Amount Of Cost
    • Yttrium Aluminum Garnet
    • Yttrium Aluminum Garnet Laser
• isbn_formats:
  • format: Print ISBN, value: 1-4244-0006-6, isbnType: Historical
• authors:
  • Author Name: K. Takahashi
    Affiliation: Semiconductor Advanced Packaging Engineering Department, Toshiba Corporation, Saiwai, Japan
    Author URL: https://ieeexplore.ieee.org/author/37065478300
    ID: 37065478300
    Order: 1
    Author Affiliations:
    • Semiconductor Advanced Packaging Engineering Department, Toshiba Corporation, Saiwai, Japan
  • Author Name: M. Sekiguchi
    Affiliation: Semiconductor Advanced Packaging Engineering Department, Toshiba Corporation, Saiwai, Japan
    Author URL: https://ieeexplore.ieee.org/author/37844565200
    ID: 37844565200
    Order: 2
    Author Affiliations:
    • Semiconductor Advanced Packaging Engineering Department, Toshiba Corporation, Saiwai, Japan

Image Sensor

• sensor_type: CMOS
• resolution: 1.3 mega pixels
• dynamic_range: not specified
• pixel_size: not specified
• dark_current: not specified

Optical Data

• focal_length: not specified
• aperture: not specified
• field_of_view: not specified
• distortion: not specified

Performance Metrics

Applications & Benefits

• cell_imaging: Applications of CMOS image sensor in digital imaging for smartphones and digital cameras.
• benefits: Benefits of using this technology for low-cost integration.

Supporting Organizations

• supported_by: Toshiba Corp., Ibiden Co. Ltd., Disco Corp., Hitachi Via Mechanics, Ltd.

Manuscript Details

• publication_date: 15-17 June 2006

Relevancy Score

• score: 8
• missing_fields:
  • dynamic_range
  • pixel_size
  • dark_current
  • focal_length
  • aperture
  • field_of_view
  • distortion
  • frame_rate
  • signal_to_noise_ratio
  • sensitivity
  • shutter_speed
  • power_consumption
  • noise

Processed JSON Filename

request_b9b3f0e8-6894-4c3c-9fcc-6df34ee55b7e-through_silicon_via_and_3d_waferchip_stacking_technology.json