Thin Layer Transfer Technologies In Heterogeneous Integration
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doi: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134342
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title: Thin Layer Transfer Technologies in
Heterogeneous Integration
- publisher: IEEE
- isbn: 979-8-3503-3417-3
- issn:
- rank: 3830
- access_type: LOCKED
- content_type: Conferences
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abstract: High performance computing, mobile
communication, automotive and IOT are driving the semiconductor
development to the next generation. Performance, power, area, cost,
time-to market, and friendly environment (PPACTE) are considered in
system-design-technology co-optimization (SDTCO) based heterogeneous
integration. Recently, chiplet, 3D-stacking, and 3D sequential
integration demonstrated some significant PPACTE benefits on the
heterogeneous integration. To innovate the diversity of chiplet design,
the universal chiplet interconnect express (UCIe) was proposed and
standardized some specifications for Si bridge, passive interposer, and
organic interposer. The D2W Cu-Cu hybrid bonding technology made the 3D
stacking possibility from logic-to-CIS to logic-to-memory. 3D sequential
integration was considered to partition the pixel cell of CMOS image
sensors (CIS) to the pixel Si layer and the pixel transistor layer. The
innovations of thin layer transfer technologies are becoming more and
more important in the heterogeneous integration future. In this
presentation, the wafer thinning technologies and the wafer bonding
technologies will be reviewed and summarized. Some thin layer transfer
integration approaches will be compared. These technology constraints on
thermal budget and quality control are also addressed.
- article_number: 10134342
-
pdf_url:
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10134342
-
html_url:
https://ieeexplore.ieee.org/document/10134342/
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abstract_url:
https://ieeexplore.ieee.org/document/10134342/
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publication_title: 2023 International VLSI Symposium on
Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
- conference_location: HsinChu, Taiwan
- conference_dates: 17-20 April 2023
- publication_number: 10133934
- is_number: 10133941
- publication_year: 2023
- publication_date: 17-20 April 2023
- start_page: 1
- end_page: 1
- citing_paper_count: 0
- citing_patent_count: 0
- download_count: 275
- insert_date: 20230531
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index_terms:
-
ieee_terms:
- Multichip modules
- Three-dimensional displays
- Very large scale integration
- Silicon
- Wafer bonding
- Transistors
- Technological innovation
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dynamic_index_terms:
- Heterogeneous Integration
- Multichip Module
- High-performance Computing
- Supercomputer
- Mobile Communication
- Mobile Telephony
- Mobile Telephone
- Mobile Telecommunications
- Thermal Budget
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isbn_formats:
-
format: Print on Demand(PoD) ISBN,
value: 979-8-3503-3417-3,
isbnType: New-2005
-
format: Electronic ISBN,
value: 979-8-3503-3416-6,
isbnType: New-2005
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authors:
Image Sensor
- sensor_type: CMOS
- resolution: not specified
- dynamic_range: not specified
- pixel_size: not specified
- dark_current: not specified
Optical Data
- focal_length: not specified
- aperture: not specified
- field_of_view: not specified
- distortion: not specified
Performance Metrics
Applications & Benefits
- cell_imaging: not specified
- benefits: not specified
Supporting Organizations
- supported_by: not specified
Manuscript Details
- publication_date: 17-20 April 2023
Relevancy Score
- score: 10
-
missing_fields:
- resolution
- dynamic_range
- pixel_size
- dark_current
- focal_length
- aperture
- field_of_view
- distortion
- frame_rate
- signal_to_noise_ratio
- sensitivity
- shutter_speed
- power_consumption
- noise
- cell_imaging
- benefits
- supported_by
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