Technology And Device Scaling Considerations For Cmos Imagers

• doi: 10.1109/16.544384
• title: Technology and device scaling considerations for CMOS imagers
• publisher: IEEE
• isbn:
• issn: 1557-9646
• rank: 3737
• access_type: LOCKED
• content_type: Journals
• abstract: This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from "standard" CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed. Our analyses suggest that while "standard" CMOS technologies may provide adequate imaging performance at the 2-1 /spl mu/m generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 /spl mu/m technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined.
• article_number: 544384
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=544384
• html_url: https://ieeexplore.ieee.org/document/544384/
• abstract_url: https://ieeexplore.ieee.org/document/544384/
• publication_title: IEEE Transactions on Electron Devices
• conference_location:
• conference_dates:
• publication_number: 16
• is_number: 11893
• publication_year: 1996
• publication_date: Dec. 1996
• start_page: 2131
• end_page: 2142
• citing_paper_count: 178
• citing_patent_count: 50
• download_count: 1476
• insert_date: 20020806
• index_terms:
  • ieee_terms:
    • CMOS technology
    • CMOS image sensors
    • Image analysis
    • Pixel
    • Performance analysis
    • CMOS process
    • Guidelines
    • Analog circuits
    • Fabrication
    • Technological innovation
  • dynamic_index_terms:
    • Scalable Technology
    • Device Scaling
    • Fabrication Process
    • Image Sensor
    • Camera Sensor
    • Impact Scale
    • CMOS Technology
    • Impact Of Devices
    • Impact Of These Devices
    • Pixel Size
    • Level Of Integration
    • Threshold Voltage
    • Boolean Logic
    • Logic Functions
    • Logic Operations
    • Parasitic Capacitance
    • Ratio Of Cases
    • Dark Current
    • P-n Junction
    • Carrier Lifetime
    • High Level Of Integration
    • Spectral Sensitivity
    • Carrier Diffusion
    • Modulation Transfer Function
    • Optical Transfer Function
    • Minimum Feature Size
    • Tunneling Current
    • Minority Carrier
    • Silicide
    • Gate Current
    • Conversion Gain
    • Substrate Contact
    • Voltage Scaling
    • Minimum Size
    • Chip Size
• authors:
  • Author Name: Hon-Sum Wong
    Affiliation: IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
    Author URL: https://ieeexplore.ieee.org/author/37087255365
    ID: 37087255365
    Order: 1
    Author Affiliations:
    • IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA

Image Sensor

• sensor_type: CMOS
• resolution: not directly specified
• dynamic_range: not directly specified
• pixel_size: down to 0.25-0.18 μm generation and beyond
• dark_current: fairly constant with technology; typical value is 5-1000 pA/cm² depending on surface quality and pixel design aspects discussed in the paper, indicates potential for increased dark noise with scaling (particularly in fully depleted SOI devices) but not quantified in general terms yet

Optical Data

• focal_length: not specified
• aperture: not specified
• field_of_view: not specified
• distortion: not specified

Performance Metrics

• signal_to_noise_ratio: not explicitly stated but a S/N ratio of 50 at 20% full signal is regarded as good performance
• power_consumption: low power consumption emphasized as a general advantage for CMOS imagers; specific values were not provided in the extracted text
• noise: mentioned as dark current shot noise, kTC noise, and 1/f noise, with associated noise factors discussed but no specific quantifications given

Applications & Benefits

• cell_imaging: CMOS imagers used for mobile applications, low-power operation making them suitable for automotive and consumer electronics, and potential for complete integration on a chip without lens
• benefits: Advantages include lower power consumption, system integration (including on-chip electronics and processing), and random access capability

Supporting Organizations

• supported_by: IBM, University collaborations, and various organizations indicated but not specifically listed

Manuscript Details

• publication_date: Dec. 1996

Relevancy Score

• score: 10
• missing_fields:
  • resolution
  • dynamic_range
  • focal_length
  • aperture
  • field_of_view
  • distortion
  • frame_rate
  • sensitivity
  • shutter_speed
  • power_consumption
  • noise

Processed JSON Filename

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