Power Reduction Of A 12Bit 40Mss Pipeline Adc Exploiting Partial Amplifier Sharing

• doi: 10.1109/DATE.2009.5090690
• title: Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
• publisher: IEEE
• isbn: 978-3-9810-8015-5
• issn: 1558-1101
• partnum: 09EX2737
• rank: 3299
• access_type: LOCKED
• content_type: Conferences
• abstract: High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35 mum CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one.
• article_number: 5090690
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5090690
• html_url: https://ieeexplore.ieee.org/document/5090690/
• abstract_url: https://ieeexplore.ieee.org/document/5090690/
• publication_title: 2009 Design, Automation & Test in Europe Conference & Exhibition
• conference_location: Nice, France
• conference_dates: 20-24 April 2009
• publication_number: 4926138
• is_number: 5090609
• publication_year: 2009
• publication_date: 20-24 April 2009
• start_page: 369
• end_page: 373
• citing_paper_count: 3
• citing_patent_count: 0
• download_count: 323
• insert_date: 20090623
• index_terms:
  • ieee_terms:
    • Pipelines
    • Power amplifiers
    • Power dissipation
    • Topology
    • High power amplifiers
    • Switches
    • Clocks
    • Signal resolution
    • Circuit noise
    • Integrated circuit synthesis
  • author_terms:
    • ADC
    • pipeline
    • CMOS
    • low-power
  • dynamic_index_terms:
    • Pipelined Analog-to-digital Converter
    • Analog-to-digital Converter
    • Analog-to-digital
    • Digital-to-analog Converter
    • Iterative Design
    • Loop Design
    • Circuitry
    • Power Consumption
    • Common Mode
    • Input Voltage
    • Thermal Noise
    • Current Noise
    • Settling Time
    • Colonial Times
    • Capacity Of Samples
    • Operational Amplifier
    • Op-amp
    • Clock Signal
    • Switched Capacitor
    • Common Topology
    • Adjacent Stages
    • Big Range
• isbn_formats:
  • format: CD, value: 978-3-9810-8015-5, isbnType: New-2005
  • format: Print ISBN, value: 978-1-4244-3781-8, isbnType: New-2005
• authors:
  • Author Name: J. A. Diaz-Madrid
    Affiliation: Integrated Circuit Design-Analog, Fraunhofer Institute of Integrated Circuits and Systems, Erlangen, Germany
    Author URL: https://ieeexplore.ieee.org/author/38275793000
    ID: 38275793000
    Order: 1
    Author Affiliations:
    • Integrated Circuit Design-Analog, Fraunhofer Institute of Integrated Circuits and Systems, Erlangen, Germany
  • Author Name: H. Neubauer
    Affiliation: Integrated Circuit Design-Analog, Fraunhofer Institute of Integrated Circuits and Systems, Erlangen, Germany
    Author URL: https://ieeexplore.ieee.org/author/37396525900
    ID: 37396525900
    Order: 2
    Author Affiliations:
    • Integrated Circuit Design-Analog, Fraunhofer Institute of Integrated Circuits and Systems, Erlangen, Germany
  • Author Name: H. Hauer
    Affiliation: Integrated Circuit Design-Analog, Fraunhofer Institute of Integrated Circuits and Systems, Erlangen, Germany
    Author URL: https://ieeexplore.ieee.org/author/37355304700
    ID: 37355304700
    Order: 3
    Author Affiliations:
    • Integrated Circuit Design-Analog, Fraunhofer Institute of Integrated Circuits and Systems, Erlangen, Germany
  • Author Name: G. Domenech-Asensi
    Affiliation: Departamento de Electrýnica y Tecnologãa de Computadoras, Universidad Politécnica de Cartagena, Cartagena, Spain
    Author URL: https://ieeexplore.ieee.org/author/38270892100
    ID: 38270892100
    Order: 4
    Author Affiliations:
    • Departamento de Electrýnica y Tecnologãa de Computadoras, Universidad Politécnica de Cartagena, Cartagena, Spain
  • Author Name: R. Ruiz-Merino
    Affiliation: Departamento de Electrýnica y Tecnologãa de Computadoras, Universidad Politécnica de Cartagena, Cartagena, Spain
    Author URL: https://ieeexplore.ieee.org/author/38271087600
    ID: 38271087600
    Order: 5
    Author Affiliations:
    • Departamento de Electrýnica y Tecnologãa de Computadoras, Universidad Politécnica de Cartagena, Cartagena, Spain

Image Sensor

• sensor_type: CMOS
• resolution: 12-bit
• dynamic_range: 3 Vpp
• pixel_size: not specified
• dark_current: not specified

Optical Data

• focal_length: not specified
• aperture: not specified
• field_of_view: not specified
• distortion: not specified

Performance Metrics

• frame_rate: 40 MS/s
• signal_to_noise_ratio: 68.7 dB
• power_consumption: 107 mW

Applications & Benefits

• cell_imaging: not specified
• benefits: Achieves good tradeoff between circuit resolution and power dissipation.

Supporting Organizations

• supported_by: Ministerio de Educación y Ciencia of Spain and the European Regional Development Fund (FEDER)

Manuscript Details

• publication_date: 20-24 April 2009

Relevancy Score

• score: 6
• missing_fields:
  • fill factor
  • quantum efficiency
  • readout speed
  • noise sources
  • design considerations

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