High Speed Cmos Vision Chips

• doi: 10.1109/MWSCAS.2011.6026285
• title: High speed CMOS vision chips
• publisher: IEEE
• isbn: 978-1-61284-855-6
• issn: 1548-3746
• partnum: 11CH38848
• rank: 2608
• access_type: LOCKED
• content_type: Conferences
• abstract: This paper presents novel high speed vision chips based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit. The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N×N) parallelism and an O(N) parallelism, respectively. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively. Prototype chips are fabricated using the 0.18μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.
• article_number: 6026285
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6026285
• html_url: https://ieeexplore.ieee.org/document/6026285/
• abstract_url: https://ieeexplore.ieee.org/document/6026285/
• publication_title: 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
• conference_location: Seoul, Korea (South)
• conference_dates: 7-10 Aug. 2011
• publication_number: 6019810
• is_number: 6026262
• publication_year: 2011
• publication_date: 7-10 Aug. 2011
• start_page: 1
• end_page: 4
• citing_paper_count: 4
• citing_patent_count: 0
• download_count: 241
• insert_date: 20110922
• index_terms:
  • ieee_terms:
    • Parallel processing
    • Complexity theory
    • Morphology
    • Image recognition
  • dynamic_index_terms:
    • High-speed CMOS
    • Vision Chips
    • Image Processing
    • Parallelization
    • Parallel Computing
    • Image Recognition
    • Image Sensor
    • Camera Sensor
    • High-level Processing
    • Higher-level Processes
    • Higher-level Cognitive Processes
    • High-level Cognitive Processes
    • Target Tracking
    • Pattern Extraction
    • CMOS Process
    • Image Resolution
    • Large Amount Of Data
    • Small Amount Of Data
    • Face Detection
    • On-chip Memory
    • Standard CMOS
    • General-purpose Computer
• isbn_formats:
  • format: Online ISBN, value: 978-1-61284-855-6, isbnType: New-2005
  • format: Print ISBN, value: 978-1-61284-856-3, isbnType: New-2005
  • format: Electronic ISBN, value: 978-1-61284-857-0, isbnType: New-2005
• authors:
  • Author Name: Nanjian Wu
    Affiliation: State Key Laboratory for Super lattices and Microstructures, Chinese Academy of Sciences, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37286754000
    ID: 37286754000
    Order: 1
    Author Affiliations:
    • State Key Laboratory for Super lattices and Microstructures, Chinese Academy of Sciences, Beijing, China

Image Sensor

• sensor_type: CMOS
• resolution: 64x64 pixels
• dynamic_range: Not specified
• pixel_size: Not specified
• dark_current: Not specified

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

• frame_rate: 1000 fps

Applications & Benefits

• cell_imaging: Not specified
• benefits: Applications include target tracking, pattern extraction, and image recognition.

Supporting Organizations

• supported_by: National Natural Science Foundation of China under Grant No. 60976023.

Manuscript Details

• publication_date: 7-10 Aug. 2011

Relevancy Score

• score: 8
• missing_fields:
  • fill factor
  • quantum efficiency
  • readout speed
  • noise sources
  • analog-to-digital conversion techniques
  • design considerations including microlenses, on-chip colour filters, global or rolling shutters, and backside illumination

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