Fabrication Of 3D Packaging Tsv Using Drie

• doi: 10.1109/DTIP.2008.4752963
• title: Fabrication of 3D packaging TSV using DRIE
• publisher: IEEE
• isbn: 978-2-35500-006-5
• issn:
• partnum: 08EX2209
• rank: 2472
• access_type: LOCKED
• content_type: Conferences
• abstract: 3D stacking of die with TSV (through Silicon Via) connection as well as wafer level packaging of CMOS image sensors (CIS) are becoming very hot topics. While TSV of CIS is definitively a back-end technique, 3D stacking of die through TSV can be done with different strategies: from the via first approach, a front-end process, to the via last approach, a back-end process. Each of these different ways of elaborating the vias has its advantages and drawbacks in terms of electrical performances, refilling materials and cost. They have in common the need to etch the vias. In this paper, we will review the DRIE performances for the definition of the different via shapes, depths, and sizes. A very low temperature (< 150 degC) PECVD process has also been characterized and will be presented for the high demanding packaging of CIS.
• article_number: 4752963
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4752963
• html_url: https://ieeexplore.ieee.org/document/4752963/
• abstract_url: https://ieeexplore.ieee.org/document/4752963/
• publication_title: 2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS
• conference_location: Nice, France
• conference_dates: 9-11 April 2008
• publication_number: 4731228
• is_number: 4752931
• publication_year: 2008
• publication_date: 9-11 April 2008
• start_page: 109
• end_page: 114
• citing_paper_count: 42
• citing_patent_count: 1
• download_count: 2035
• insert_date: 20090119
• index_terms:
  • ieee_terms:
    • Fabrication
    • Packaging
    • Through-silicon vias
    • Computational Intelligence Society
    • Wafer scale integration
    • Stacking
    • Silicon
    • CMOS image sensors
    • Costs
    • Etching
  • author_terms:
    • TSV
    • Via first
    • Via last
    • Packaging
    • DRIE
    • Silicon etching
    • Bosch process
    • Tapered profile
    • Oxide etching
    • PECVD
  • dynamic_index_terms:
    • Through Silicon Via
    • Back-end Processing
    • Aspect Ratio
    • Fabrication Process
    • Oxide Layer
    • Layer Deposition
    • High Aspect Ratio
    • Microfabrication
    • Micromachining
    • Dielectric Layer
    • Insulation Layer
    • Uniform Temperature
    • Silicon-on-insulator
    • Buried Oxide
    • Halogen Groups
    • Halide Groups
    • Fluorine Groups
    • Machine System
    • Etching Rate
    • High-density Plasma
• isbn_formats:
  • format: Print ISBN, value: 978-2-35500-006-5, isbnType: New-2005
• authors:
  • Author Name: M. Puech
    Affiliation: Alcatel Micro Machining Systems, Annecy-le-Vieux, France
    Author URL: https://ieeexplore.ieee.org/author/37419016700
    ID: 37419016700
    Order: 1
    Author Affiliations:
    • Alcatel Micro Machining Systems, Annecy-le-Vieux, France
  • Author Name: J.M. Thevenoud
    Affiliation: Alcatel Micro Machining Systems, Annecy-le-Vieux, France
    Author URL: https://ieeexplore.ieee.org/author/37662341700
    ID: 37662341700
    Order: 2
    Author Affiliations:
    • Alcatel Micro Machining Systems, Annecy-le-Vieux, France
  • Author Name: J.M. Gruffat
    Affiliation: Alcatel Micro Machining Systems, Annecy-le-Vieux, France
    Author URL: https://ieeexplore.ieee.org/author/37662342300
    ID: 37662342300
    Order: 3
    Author Affiliations:
    • Alcatel Micro Machining Systems, Annecy-le-Vieux, France
  • Author Name: N. Launay
    Affiliation: Alcatel Micro Machining Systems, Annecy-le-Vieux, France
    Author URL: https://ieeexplore.ieee.org/author/37662341900
    ID: 37662341900
    Order: 4
    Author Affiliations:
    • Alcatel Micro Machining Systems, Annecy-le-Vieux, France
  • Author Name: N. Arnal
    Affiliation: Alcatel Micro Machining Systems, Annecy-le-Vieux, France
    Author URL: https://ieeexplore.ieee.org/author/37085446873
    ID: 37085446873
    Order: 5
    Author Affiliations:
    • Alcatel Micro Machining Systems, Annecy-le-Vieux, France
  • Author Name: P. Godinat
    Affiliation: Alcatel Micro Machining Systems, Annecy-le-Vieux, France
    Author URL: https://ieeexplore.ieee.org/author/37662344800
    ID: 37662344800
    Order: 6
    Author Affiliations:
    • Alcatel Micro Machining Systems, Annecy-le-Vieux, France

Image Sensor

• sensor_type: CMOS
• resolution: not specified
• dynamic_range: not specified
• pixel_size: not specified
• dark_current: not specified

Optical Data

• focal_length: not specified
• aperture: not specified
• field_of_view: not specified
• distortion: not specified

Performance Metrics

Applications & Benefits

• cell_imaging: used in CMOS image sensors (CIS) for high-performance applications
• benefits: high demand for smaller size packages and higher memory density in devices like smartphones and medical systems

Supporting Organizations

• supported_by: Alcatel MicroMachining Systems, EMC3D consortium, STMicroelectronics

Manuscript Details

• publication_date: 9-11 April 2008

Relevancy Score

• score: 8
• missing_fields:
  • resolution
  • dynamic_range
  • pixel_size
  • dark_current
  • focal_length
  • aperture
  • field_of_view
  • distortion
  • frame_rate
  • signal_to_noise_ratio
  • sensitivity
  • shutter_speed
  • power_consumption
  • noise

Processed JSON Filename

request_b722e926-26af-4887-a52d-35ad0b8decb5-fabrication_of_3d_packaging_tsv_using_drie.json