An Onchip Binaryweight Convolution Cmos Image Sensor For Neural Networks
- doi: 10.1109/TIE.2020.3001838
-
title: An On-Chip Binary-Weight Convolution CMOS Image
Sensor for Neural Networks
- publisher: IEEE
- isbn:
- issn: 1557-9948
- rank: 1519
- access_type: LOCKED
- content_type: Journals
-
abstract: A CMOS image sensor (CIS) that can perform
on-chip binary convolution is presented. The CIS can greatly reduce
memory usage and computational complexity by directly generating a
feature map for a binary neural network. The pixel readout of the CIS is
performed in the column-parallel fashion using incremental delta-sigma
analog-to-digital converters (ADCs). The CIS operates in two different
modes: convolution and normal modes. When the column ADC is working in
the convolution mode, it works as a first-order delta-sigma ADC and
generates convolved images using a binary kernel. In the normal
operation mode, the ADC is switched to a second-order delta-sigma ADC
with little hardware modification and used to capture high-quality
images. To demonstrate the CIS architecture, a 192 × 128-pixel CIS,
which occupies an active die area of 14.44 mm2, is fabricated in a 0.18
μm standard CMOS process. The performance of the CIS is evaluated
through measurements and network simulations. In the normal operation
mode, the CIS achieves a read noise of 14.79 e-rms and a full-well
capacity of 6,420 e- with a resulting dynamic range of 53 dB. The power
consumptions of the CIS are 49.2 and 52.5 mW during the normal and
convolution modes, respectively.
- article_number: 9119774
-
pdf_url:
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9119774
-
html_url:
https://ieeexplore.ieee.org/document/9119774/
-
abstract_url:
https://ieeexplore.ieee.org/document/9119774/
-
publication_title: IEEE Transactions on Industrial
Electronics
- conference_location:
- conference_dates:
- publication_number: 41
- is_number: 9420632
- publication_year: 2021
- publication_date: Aug. 2021
- start_page: 7567
- end_page: 7576
- citing_paper_count: 12
- citing_patent_count: 0
- download_count: 1611
- insert_date: 20200617
-
index_terms:
-
ieee_terms:
- Kernel
- Convolution
- Quantization (signal)
- Modulation
- Neural networks
- Field programmable gate arrays
- Application specific integrated circuits
-
author_terms:
- Binary weight neural network
- CMOS image sensor
- convolution operation
- incremental delta-sigma analog-to-digital converter
-
dynamic_index_terms:
- Neural Network
- Feature Maps
- Operation Mode
- Analog-to-digital Converter
- Analog-to-digital
- Digital-to-analog Converter
- Memory Usage
- Simulated Networks
- Hardware Modifications
- Convolutional Network
- Convolutional Neural Network
- Network Layer
- Convolution Operation
- Convolution Kernel
- Classification Rate
- Classification Evaluation
- Digital Signal
- Root Mean Square Values
- Rms Value
- Root-mean-square Values
- Quantization Error
- Amount Of Error
- Quantization Noise
- Circuit Implementation
- Output Pixel
- Digital Output
- Kernel Values
- Readout Circuit
- Integrator Output
- Tungsten Halogen
- Tungsten Halogen Lamp
- Tungsten-halogen
- Tungsten-halogen Lamp
- Tungsten Halogen Light
- Digital Integration
- Parasitic Capacitance
- Input Samples
- Noise Amplification
-
authors:
-
Author Name: Woo-Tae Kim
Affiliation: School of Electrical Engineering and
Computer Science, Gwangju Institute of Science and Technology,
Gwangju, South Korea
Author URL:
https://ieeexplore.ieee.org/author/37086270747
ID: 37086270747
Order: 1
Author Affiliations:
-
School of Electrical Engineering and Computer Science, Gwangju
Institute of Science and Technology, Gwangju, South Korea
-
Author Name: Hyunkeun Lee
Affiliation: School of Electrical Engineering and
Computer Science, Gwangju Institute of Science and Technology,
Gwangju, South Korea
Author URL:
https://ieeexplore.ieee.org/author/37086263856
ID: 37086263856
Order: 2
Author Affiliations:
-
School of Electrical Engineering and Computer Science, Gwangju
Institute of Science and Technology, Gwangju, South Korea
-
Author Name: Jung-Gyun Kim
Affiliation: School of Electrical Engineering and
Computer Science, Gwangju Institute of Science and Technology,
Gwangju, South Korea
Author URL:
https://ieeexplore.ieee.org/author/37086919924
ID: 37086919924
Order: 3
Author Affiliations:
-
School of Electrical Engineering and Computer Science, Gwangju
Institute of Science and Technology, Gwangju, South Korea
-
Author Name: Byung-Geun Lee
Affiliation: School of Electrical Engineering and
Computer Science, Gwangju Institute of Science and Technology,
Gwangju, South Korea
Author URL:
https://ieeexplore.ieee.org/author/38240871700
ID: 38240871700
Order: 4
Author Affiliations:
-
School of Electrical Engineering and Computer Science, Gwangju
Institute of Science and Technology, Gwangju, South Korea
Image Sensor
- sensor_type: CMOS
- resolution: 192x128 pixels
- dynamic_range: 53 dB
- pixel_size: Not specified
- dark_current: Not specified
Optical Data
- focal_length: 8 mm
- aperture: Not specified
- field_of_view: Not specified
- distortion: Not specified
Performance Metrics
-
power_consumption: 49.2 mW (normal mode), 52.5 mW
(convolution mode)
- noise: 14.79 e-rms
Applications & Benefits
-
cell_imaging: Used in image recognition applications
such as self-driving vehicles, surveillance, biomedical diagnosis.
-
benefits: Reduces memory usage and computational
complexity by generating feature maps directly on the chip.
Supporting Organizations
-
supported_by: MOTIE Research Grant 2020, MSIT (Ministry
of Science and ICT), Korea
Manuscript Details
- publication_date: Aug. 2021
Relevancy Score
- score: 10
-
missing_fields:
- pixel_size
- fill_factor
- quantum_efficiency
- dark_current
- readout_speed
- noise_sources
- microlenses
- on-chip colour filters
- global or rolling shutters
- backside illumination
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