An Areaefficient And Lowpower 12B Sarsingleslope Adc Without Calibration Method For Cmos Image Sensors

• doi: 10.1109/TED.2016.2587721
• title: An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors
• publisher: IEEE
• isbn:
• issn: 1557-9646
• rank: 1481
• access_type: LOCKED
• content_type: Journals
• abstract: This paper presents an area-efficient and low-power 12-b successive approximation register/single-slope analog-todigital converter (SAR/SS ADC) for CMOS image sensor (CIS) applications. The number of unit capacitors of the proposed SAR/SS ADC is reduced to 1/64th of that of a conventional 12-b SAR ADC using only a 6-b capacitor digital-to-analog converter (DAC) and the power consumption is reduced by sharing analog circuits between the SAR ADC and the SS ADC. In addition, the proposed ADC properly operates without using any calibration method as it is designed to be robust to inaccuracies in analog circuits by connecting the ramp signal to the bottom plate of the unit capacitor in the capacitor DAC. A 1936 × 840 pixel 60 frames/s CIS with the proposed SAR/SS ADCs was fabricated using a 90-nm CMOS process, and each readout channel with the proposed SAR/SS ADC occupies an area of 2.24 μm × 998 μm and consumes a power of 30 μW. The measurement results show that the SAR/SS ADC has a differential nonlinearity of -0.45/+0.84 LSB and an integral nonlinearity of -1.5/+0.74 LSB. In addition, the developed CIS has a temporal noise of 2.7 LSBrms and a column fixed pattern noise of 0.07 LSB.
• article_number: 7515162
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7515162
• html_url: https://ieeexplore.ieee.org/document/7515162/
• abstract_url: https://ieeexplore.ieee.org/document/7515162/
• publication_title: IEEE Transactions on Electron Devices
• conference_location:
• conference_dates:
• publication_number: 16
• is_number: 7548080
• publication_year: 2016
• publication_date: Sept. 2016
• start_page: 3599
• end_page: 3604
• citing_paper_count: 43
• citing_patent_count: 2
• download_count: 4530
• insert_date: 20160718
• index_terms:
  • ieee_terms:
    • Capacitors
    • Power demand
    • Analog-digital conversion
    • Generators
    • Calibration
    • Timing
    • CMOS image sensors
  • author_terms:
    • CMOS image sensor (CIS)
    • column-parallel readout
    • hybrid analog-to-digital converter (ADC)
    • single-slope (SS) ADC
    • successive approximation ADC
  • dynamic_index_terms:
    • Calibration Method
    • Power Consumption
    • Analog-to-digital Converter
    • Analog-to-digital
    • Digital-to-analog Converter
    • Plate Capacitor
    • Temporal Noise
    • Number Of Capacitors
    • Mobile App
    • Mobile Application
    • Smartphone Application
    • Smartphone App
    • Control Signal
    • Dark Conditions
    • Signal Variability
    • Figure Of Merit
    • Digital Signal
    • Parasitic Capacitance
    • Sensor Output
    • Error Size
    • Conversion Time
    • Least Significant Bit
    • Low Bit
    • Most Significant Bit
    • High Bit
    • Highest Bit
    • Operational Amplifier
    • Op-amp
    • Conversion Step
    • Sense Amplifier
    • Pixel Array
    • Readout Circuit
    • Output Buffer
• authors:
  • Author Name: Min-Kyu Kim
    Affiliation: Department of Electronics and Computer Engineering, Hanyang University, Seoul, South Korea
    Author URL: https://ieeexplore.ieee.org/author/37349829800
    ID: 37349829800
    Order: 1
    Author Affiliations:
    • Department of Electronics and Computer Engineering, Hanyang University, Seoul, South Korea
  • Author Name: Seong-Kwan Hong
    Affiliation: Department of Electronics and Computer Engineering, Hanyang University, Seoul, South Korea
    Author URL: https://ieeexplore.ieee.org/author/37085359277
    ID: 37085359277
    Order: 2
    Author Affiliations:
    • Department of Electronics and Computer Engineering, Hanyang University, Seoul, South Korea
  • Author Name: Oh-Kyong Kwon
    Affiliation: Department of Electronics and Computer Engineering, Hanyang University, Seoul, South Korea
    Author URL: https://ieeexplore.ieee.org/author/37276791400
    ID: 37276791400
    Order: 3
    Author Affiliations:
    • Department of Electronics and Computer Engineering, Hanyang University, Seoul, South Korea

Image Sensor

• sensor_type: CMOS
• resolution: 1936x840
• dynamic_range: 62 dB
• pixel_size: 1.12 µm
• dark_current: Not specified

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

• frame_rate: 60 fps
• power_consumption: 30 µW
• noise: Temporal noise: 2.7 LSB rms; Column fixed pattern noise: 0.07 LSB rms.

Applications & Benefits

• cell_imaging: Suitable for high-speed CMOS image sensor applications.
• benefits: Area-efficient, low power consumption whilke providing high-resolution imaging without the need for calibration.

Supporting Organizations

• supported_by: SK Hynix Semiconductor Inc., Hanyang University

Manuscript Details

• publication_date: Sept. 2016

Relevancy Score

• score: 9
• missing_fields:
  • fill factor
  • quantum efficiency
  • readout speed
  • noise sources

Processed JSON Filename

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