A Twostep Prediction Adc Architecture For Integrated Low Power Image Sensors

• doi: 10.1109/TCSI.2016.2603519
• title: A Two-Step Prediction ADC Architecture for Integrated Low Power Image Sensors
• publisher: IEEE
• isbn:
• issn: 1558-0806
• rank: 974
• access_type: LOCKED
• content_type: Journals
• abstract: This paper presents a two-step prediction method for the design of low-power column-parallel analog-to-digital converters (ADC) in CMOS image sensors. The proposed prediction method takes advantage of the spatial likelihood of natural scenes, which shows strong correlations between neighboring pixels in the image. Based on this property, the proposed method predicts the MSBs of the selected pixel using quantization results of the neighboring pixels in the previous row, which enables a significant power reduction of the A/D conversions. The simulation results show that up to 20∼30% power saving can be achieved for most natural scenes. A 384 $\times$ 256-pixel prototype chip was fabricated using a 0.35 $\mu\text{m}$ CMOS technology with a pixel footprint of $15\ \mu\text{m} \times 15\ \mu\text{m}$. The fill factor is 49%. 10-bit successive approximation register (SAR) ADCs are used in the column-parallel ADC array.
• article_number: 7588085
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7588085
• html_url: https://ieeexplore.ieee.org/document/7588085/
• abstract_url: https://ieeexplore.ieee.org/document/7588085/
• publication_title: IEEE Transactions on Circuits and Systems I: Regular Papers
• conference_location:
• conference_dates:
• publication_number: 8919
• is_number: 7809129
• publication_year: 2017
• publication_date: Jan. 2017
• start_page: 50
• end_page: 60
• citing_paper_count: 24
• citing_patent_count: 0
• download_count: 2508
• insert_date: 20161011
• index_terms:
  • ieee_terms:
    • Analog-digital conversion
    • Prediction algorithms
    • CMOS image sensors
    • Power dissipation
    • Capacitors
    • Algorithm design and analysis
  • author_terms:
    • CMOS image sensor
    • column-parallel ADC
    • common MSBs
    • low power
    • prediction
  • dynamic_index_terms:
    • Image Sensor
    • Camera Sensor
    • Low Power Images
    • Analog-to-digital Converter Architecture
    • Image Pixels
    • Analog-to-digital Converter
    • Analog-to-digital
    • Digital-to-analog Converter
    • Fill Factor
    • Neighboring Pixels
    • Neighborhood Pixels
    • Most Significant Bit
    • High Bit
    • Highest Bit
    • CMOS Technology
    • Power Consumption
    • Photodetector
    • Predictor Of Success
    • Specific Imaging
    • Least Significant Bit
    • Low Bit
    • Local Implementation
    • Binary Search
    • Digital Circuits
    • Digital Circuitry
    • Values In Row
    • Values In Each Row
    • Pixel Array
    • Wrong Predictions
    • Digital Value
    • Switching Energy
    • Power Supply Voltage
    • Global Implementation
    • Analogous Values
    • Parallel Values
    • Extra Circuit
    • Silicon Area
    • Two-step Algorithm
    • Judgment Process
    • Signal Readout
• authors:
  • Author Name: Hang Yu
    Affiliation: VIRTUS IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
    Author URL: https://ieeexplore.ieee.org/author/37089736693
    ID: 37089736693
    Order: 1
    Author Affiliations:
    • VIRTUS IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
  • Author Name: Wei Tang
    Affiliation: Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA
    Author URL: https://ieeexplore.ieee.org/author/37085633088
    ID: 37085633088
    Order: 2
    Author Affiliations:
    • Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA
  • Author Name: Menghan Guo
    Affiliation: VIRTUS IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
    Author URL: https://ieeexplore.ieee.org/author/37085361629
    ID: 37085361629
    Order: 3
    Author Affiliations:
    • VIRTUS IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
  • Author Name: Shoushun Chen
    Affiliation: VIRTUS IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
    Author URL: https://ieeexplore.ieee.org/author/37535877300
    ID: 37535877300
    Order: 4
    Author Affiliations:
    • VIRTUS IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore

Image Sensor

• sensor_type: CMOS
• resolution: 384 × 256
• dynamic_range: Not specified
• pixel_size: 15 μm × 15 μm
• dark_current: Not specified

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

• power_consumption: 463 pJ/pixel

Applications & Benefits

• cell_imaging: Used in smartphones, medical devices, and automotive systems.
• benefits: Low power consumption and significant energy savings through two-step prediction ADC architecture.

Supporting Organizations

• supported_by: MOE2012-T2-2-124 (ARC 17/13), RG 100/14 (2014-T1-001-105), U.S. NSF ECCS-1408019.

Manuscript Details

• publication_date: Jan. 2017

Relevancy Score

• score: 9
• missing_fields:
  • quantum_efficiency
  • readout_speed
  • temporal_noise
  • fixed_pattern_noise
  • microlenses
  • on_chip_colour_filters
  • global_shutter
  • rolling_shutter
  • backside_illumination

Processed JSON Filename

request_5f8a5d68-4fb0-4245-bfe2-7530d150b0ca-a_twostep_prediction_adc_architecture_for_integrated_low_power_image_sensors.json