A Stacked Cmos Image Sensor With Arrayparallel Adc Architecture

• doi: 10.1109/JSSC.2017.2784759
• title: A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture
• publisher: IEEE
• isbn:
• issn: 1558-173X
• rank: 936
• access_type: LOCKED
• content_type: Journals
• abstract: This paper presents a 4.1 megapixel, 280 frames/s, back-illuminated, stacked, global shutter (GS) CMOS image sensor with array-parallel analog-to-digital converter (ADC) architecture for region-control applications. The sensor solves an image distortion problem caused by rolling shutter in a pixel sub-array by utilizing a floating diffusion (FD) memory to implement GS operation. A newly developed circuit technique, the combination of active reset and frame correlated double sampling (CDS) operation, cancels Vth variation of pixel amplifier transistors as well as kTC noise. The active reset scheme suppresses output voltage variation of the pixel source follower. The chip supports 24-dB analog gain using a single-slope ADC and achieves 2.4e-rms readout noise in the FD-memory-based GS. An intelligent sensor system with face detection derived from low-resolution images triggering high-resolution region-of-interest (ROI) output has been demonstrated with significantly reduced data bandwidth and low ADC power dissipation by utilizing the flexible area access function.
• article_number: 8299554
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8299554
• html_url: https://ieeexplore.ieee.org/document/8299554/
• abstract_url: https://ieeexplore.ieee.org/document/8299554/
• publication_title: IEEE Journal of Solid-State Circuits
• conference_location:
• conference_dates:
• publication_number: 4
• is_number: 8325040
• publication_year: 2018
• publication_date: April 2018
• start_page: 1061
• end_page: 1070
• citing_paper_count: 20
• citing_patent_count: 0
• download_count: 4715
• insert_date: 20180221
• index_terms:
  • ieee_terms:
    • Transistors
    • Sensor arrays
    • Distortion
    • Image sensors
    • Logic gates
  • author_terms:
    • 3-D integration
    • analog-to-digital converter (ADC)
    • array-parallel ADC
    • back illuminated
    • block-parallel ADC
    • global shutter (GS)
    • high frame rate
    • low noise
    • region control
    • region of interest (ROI)
    • stacked
  • dynamic_index_terms:
    • Image Sensor
    • Camera Sensor
    • Intelligent Systems
    • Image Distortion
    • Lens Distortion
    • Radial Distortion
    • Image Deformation
    • Low-resolution Images
    • Network Bandwidth
    • Data Bandwidth
    • Modulation Bandwidth
    • Internet Bandwidth
    • Face Detection
    • Rolling Shutter
    • Solid Line
    • Horizontal Line
    • Vertical Line
    • Internet Of Things
    • Internet-of-Things
    • Control Signal
    • Frame Rate
    • High Gain
    • Negative Feedback Loop
    • Data Frame
    • Phase Noise
    • Phase-locked Loop
    • Phase Locked Loop
    • Gain Settings
    • Scanning Direction
    • Stacking Structure
    • Pixel Pitch
    • Pixel Array
    • Feedback Phase
    • Feedback Path
    • Output Pixel
    • Vertical Path
    • Conventional Architecture
    • Photodiode
    • Signal-to-noise
    • Signal-to-noise Ratio
    • Signal To Noise
    • Signal To Noise Ratio
• authors:
  • Author Name: Tomohiro Takahashi
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37961403900
    ID: 37961403900
    Order: 1
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Yuichi Kaji
    Affiliation: Sony Electronics Inc., San Jose, CA, USA
    Author URL: https://ieeexplore.ieee.org/author/37086029359
    ID: 37086029359
    Order: 2
    Author Affiliations:
    • Sony Electronics Inc., San Jose, CA, USA
  • Author Name: Yasunori Tsukuda
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086018392
    ID: 37086018392
    Order: 3
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Shinichiro Futami
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086028413
    ID: 37086028413
    Order: 4
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Katsuhiko Hanzawa
    Affiliation: Sony Electronics Inc., San Jose, CA, USA
    Author URL: https://ieeexplore.ieee.org/author/38232173400
    ID: 38232173400
    Order: 5
    Author Affiliations:
    • Sony Electronics Inc., San Jose, CA, USA
  • Author Name: Takahito Yamauchi
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37088040808
    ID: 37088040808
    Order: 6
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Ping Wah Wong
    Affiliation: Sony Electronics Inc., San Jose, CA, USA
    Author URL: https://ieeexplore.ieee.org/author/37086023291
    ID: 37086023291
    Order: 7
    Author Affiliations:
    • Sony Electronics Inc., San Jose, CA, USA
  • Author Name: Frederick T. Brady
    Affiliation: Sony Electronics Inc., San Jose, CA, USA
    Author URL: https://ieeexplore.ieee.org/author/37086022233
    ID: 37086022233
    Order: 8
    Author Affiliations:
    • Sony Electronics Inc., San Jose, CA, USA
  • Author Name: Phil Holden
    Affiliation: Sony Electronics Inc., San Jose, CA, USA
    Author URL: https://ieeexplore.ieee.org/author/37086024992
    ID: 37086024992
    Order: 9
    Author Affiliations:
    • Sony Electronics Inc., San Jose, CA, USA
  • Author Name: Thomas Ayers
    Affiliation: Sony Electronics Inc., San Jose, CA, USA
    Author URL: https://ieeexplore.ieee.org/author/37086021148
    ID: 37086021148
    Order: 10
    Author Affiliations:
    • Sony Electronics Inc., San Jose, CA, USA
  • Author Name: Kyohei Mizuta
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37392936200
    ID: 37392936200
    Order: 11
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Susumu Ohki
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086025031
    ID: 37086025031
    Order: 12
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Keiji Tatani
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37086017179
    ID: 37086017179
    Order: 13
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Hayato Wakabayashi
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37830445700
    ID: 37830445700
    Order: 14
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan
  • Author Name: Yoshikazu Nitta
    Affiliation: Sony Semiconductor Solutions Corporation, Atsugi, Japan
    Author URL: https://ieeexplore.ieee.org/author/37089133076
    ID: 37089133076
    Order: 15
    Author Affiliations:
    • Sony Semiconductor Solutions Corporation, Atsugi, Japan

Image Sensor

• sensor_type: CMOS
• resolution: 4.1 megapixels (2360 × 1728)
• dynamic_range: 24 dB
• pixel_size: 4.8 µm
• dark_current: Not specified in detail; implied low due to back-illuminated structure

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

• frame_rate: 280 frames/s
• signal_to_noise_ratio: Not specified; 2.4 e− rms readout noise
• sensitivity: 28,400 e−/lx·s
• power_consumption: 1.34 W at full frame rate (GS readout)
• noise: 2.4 e− rms (GS mode), 1.7 e− rms (RS mode)

Applications & Benefits

• cell_imaging: Region-of-interest (ROI) output for intelligent sensor system that uses face detection, allowing for high-resolution imaging in selected areas while reducing bandwidth.
• benefits: Reduced data bandwidth and low ADC power dissipation through flexible area access and ROI functionality.

Supporting Organizations

• supported_by: Sony Semiconductor Solutions Corporation

Manuscript Details

• publication_date: April 2018

Relevancy Score

• score: 10
• missing_fields:
  • focal_length
  • aperture
  • field_of_view
  • distortion

Processed JSON Filename

request_33effa3f-8d47-415f-9bc4-dc8ae08e0892-a_stacked_cmos_image_sensor_with_arrayparallel_adc_architecture.json