A Programmable Vision Chip Based On Multiple Levels Of Parallel Processors

• doi: 10.1109/JSSC.2011.2158024
• title: A Programmable Vision Chip Based on Multiple Levels of Parallel Processors
• publisher: IEEE
• isbn:
• issn: 1558-173X
• rank: 887
• access_type: LOCKED
• content_type: Journals
• abstract: This paper proposes a novel programmable vision chip based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit (MPU). The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N × N) parallelism and an O(N) parallelism, respectively. The PE array and RPs can be reconfigured to handle algorithms with different complexities and processing speeds. The PE array, RPs and MPU can execute low-, mid-and high-level image processing algorithms, respectively, which efficiently increases the performance of the vision chip. The vision chip can satisfy flexibly the needs of different vision applications such as image pre-processing, complicated feature extraction and over 1000 fps high-speed image capture. A prototype chip with 128 × 28 image sensor, 128 A/D converters, 32 8-bit RPs and 32 × 128 PEs is fabricated using the 0.18 μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.
• article_number: 5936648
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5936648
• html_url: https://ieeexplore.ieee.org/document/5936648/
• abstract_url: https://ieeexplore.ieee.org/document/5936648/
• publication_title: IEEE Journal of Solid-State Circuits
• conference_location:
• conference_dates:
• publication_number: 4
• is_number: 5995181
• publication_year: 2011
• publication_date: Sept. 2011
• start_page: 2132
• end_page: 2147
• citing_paper_count: 84
• citing_patent_count: 2
• download_count: 1962
• insert_date: 20110630
• index_terms:
  • ieee_terms:
    • Arrays
    • Pixel
    • Program processors
    • Image processing
    • Parallel processing
    • Image sensors
    • Algorithm design and analysis
  • author_terms:
    • CMOS sensor
    • image recognition
    • massive parallel
    • SIMD
    • vision chip
  • dynamic_index_terms:
    • Parallelization
    • Parallel Computing
    • Vision Chips
    • Image Processing
    • Processing Speed
    • Psychomotor Speed
    • Processing Algorithms
    • Image Recognition
    • Image Sensor
    • Camera Sensor
    • Vision Applications
    • Target Tracking
    • Image Processing Algorithms
    • High-speed Imaging
    • High Speed
    • Image Features
    • Imaging Characteristics
    • Image Pixels
    • Image Size
    • Inverter
    • Pixel Area
    • Mapping Relationship
    • Sensor Array
    • Pixel Data
    • Data For Each Pixel
    • Complicated Algorithms
    • Bitwise Operations
    • Bit Operations
    • Sensor Pixel
    • Nature Of The Algorithm
    • Arithmetic Operations
    • Basic Arithmetic
    • Chip Area
    • Average Pixel Value
    • Image Histogram
    • Grayscale Histogram
    • Sensor Resolution
• authors:
  • Author Name: Wancheng Zhang
    Affiliation: State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37291412900
    ID: 37291412900
    Order: 1
    Author Affiliations:
    • State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
  • Author Name: Qiuyu Fu
    Affiliation: State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37708519000
    ID: 37708519000
    Order: 2
    Author Affiliations:
    • State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
  • Author Name: Nan-Jian Wu
    Affiliation: State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37286754000
    ID: 37286754000
    Order: 3
    Author Affiliations:
    • State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China

Image Sensor

• sensor_type: CMOS
• resolution: 128x128
• dynamic_range: Not specified
• pixel_size: Not specified
• dark_current: Not specified

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

• frame_rate: 1000 fps
• power_consumption: 350–450 mW

Applications & Benefits

• cell_imaging: The vision chip is suitable for various applications such as target tracking, pattern extraction, and image recognition.
• benefits: The integration of the image sensor with multiple levels of parallel processors enhances processing speed and flexibility of the vision chip.

Supporting Organizations

• supported_by: National Natural Science Foundation of China, Chinese National High-Tech Researching and Development Project, Major State Basic Research Project 2011CB932902 of China

Manuscript Details

• publication_date: Sept. 2011

Relevancy Score

• score: 8
• missing_fields:
  • fill factor
  • quantum efficiency
  • readout speed
  • temporal noise
  • fixed-pattern noise
  • analog-to-digital conversion techniques
  • use of microlenses
  • on-chip colour filters
  • global or rolling shutters
  • backside illumination

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