A New Twostep Architecture Columnparallel Adc For Cmos Image Sensor

• doi: 10.1109/SBCCI.2016.7724065
• title: A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor
• publisher: IEEE
• isbn: 978-1-5090-2737-8
• issn:
• rank: 1201
• access_type: LOCKED
• content_type: Conferences
• abstract: The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two-step design. A solution is to use the same hardware twice to perform both steps. This paper proposes a 14-b, 100 kHz Nyquist frequency, two-step incremental ΣΔ (IΣΔ) analog-to-digital converter suitable for column-parallel CIS. Several architectures with different modulator order are compared to determine the most promising one. The proposed architecture, compared to a one-step second order modulator, reduces the total oversampling ratio (OSR) from 150 to 60 to reach a resolution of 14-b. The operational transconductance amplifiers (OTA) is the most critical part in our ADCs. Its required DC-gain is around 80 dB for a 120 MHz gain-bandwidth product (GBW). The ideal DNL and INL of our two-step IΣΔ ADC are respectively +0.55/-0.6 LSB and +0.5/-0.5 LSB. This work achieves a SNDR of 89 dB when a full scale sinusoid of 100 kHz is applied.
• article_number: 7724065
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7724065
• html_url: https://ieeexplore.ieee.org/document/7724065/
• abstract_url: https://ieeexplore.ieee.org/document/7724065/
• publication_title: 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)
• conference_location: Belo Horizonte, Brazil
• conference_dates: 29 Aug.-3 Sept. 2016
• publication_number: 7593174
• is_number: 7724036
• publication_year: 2016
• publication_date: 29 Aug.-3 Sept. 2016
• start_page: 1
• end_page: 6
• citing_paper_count: 2
• citing_patent_count: 0
• download_count: 856
• insert_date: 20161031
• index_terms:
  • ieee_terms:
    • Modulation
    • Gain
    • Clocks
    • Computer architecture
    • Image resolution
    • CMOS image sensors
    • Hardware
  • author_terms:
    • ADC
    • incremental
    • sigma-delta (ΣΔ)
    • two-step
    • CMOS Image Sensor
    • column-parallel ADC
    • second-order ΣΔ
  • dynamic_index_terms:
    • Image Sensor
    • Camera Sensor
    • Analog-to-digital Converter
    • Analog-to-digital
    • Digital-to-analog Converter
    • Critical Part
    • Settling Time
    • Colonial Times
    • Clock Frequency
    • Integration Of Inputs
    • Clock Cycles
    • Slew Rate
    • DC Gain
    • Integrator Output
• isbn_formats:
  • format: Print on Demand(PoD) ISBN, value: 978-1-5090-2737-8, isbnType: New-2005
  • format: Electronic ISBN, value: 978-1-5090-2736-1, isbnType: New-2005
• authors:
  • Author Name: Pierre Bisiaux
    Affiliation: GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
    Author URL: https://ieeexplore.ieee.org/author/37085899341
    ID: 37085899341
    Order: 1
    Author Affiliations:
    • GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
  • Author Name: Caroline Lelandais-Perrault
    Affiliation: GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
    Author URL: https://ieeexplore.ieee.org/author/38270258000
    ID: 38270258000
    Order: 2
    Author Affiliations:
    • GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
  • Author Name: Anthony Kolar
    Affiliation: GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
    Author URL: https://ieeexplore.ieee.org/author/37547576800
    ID: 37547576800
    Order: 3
    Author Affiliations:
    • GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
  • Author Name: Philippe Benabes
    Affiliation: GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
    Author URL: https://ieeexplore.ieee.org/author/37269355100
    ID: 37269355100
    Order: 4
    Author Affiliations:
    • GeePs, UPMC Univ Paris 06, Gif sur Yvette CEDEX, France
  • Author Name: Filipe Vinci Dos Santos
    Affiliation: Advanced Analog Design Group, CentraleSupelec, 3, rue Joliot CuriePlateau de Moulon, France
    Author URL: https://ieeexplore.ieee.org/author/37085900173
    ID: 37085900173
    Order: 5
    Author Affiliations:
    • Advanced Analog Design Group, CentraleSupelec, 3, rue Joliot CuriePlateau de Moulon, France

Image Sensor

• sensor_type: CMOS
• resolution: 1920x1080
• dynamic_range: Not explicitly mentioned
• pixel_size: Not explicitly mentioned
• dark_current: Not explicitly mentioned

Optical Data

• focal_length: Not explicitly mentioned
• aperture: Not explicitly mentioned
• field_of_view: Not explicitly mentioned
• distortion: Not explicitly mentioned

Performance Metrics

• frame_rate: 100 fps
• signal_to_noise_ratio: 89 dB
• sensitivity: Not explicitly mentioned
• shutter_speed: Not explicitly mentioned
• power_consumption: 450 µW
• noise: Not explicitly mentioned

Applications & Benefits

• cell_imaging: High quality CMOS image sensors (CIS) have become indispensable in the aerospace field, suitable for various applications including smartphones, medical devices, and automotive systems.
• benefits: The proposed architecture allows for monolithic integration of the whole CIS, achieving high resolution while managing power consumption effectively.

Supporting Organizations

• supported_by: GeePs I Group 01' electrical engineering -Paris, UMR CNRS 8507, CentraleSupelec, Univ Paris-Sud, Universite Paris-Saclay, Sorbonne Universites, UPMC Univ Paris 06

Manuscript Details

• publication_date: 29 Aug.-3 Sept. 2016

Relevancy Score

• score: 9
• missing_fields:
  • fill factor
  • quantum efficiency
  • readout speed
  • noise sources
  • microlenses
  • on-chip colour filters
  • global or rolling shutters
  • backside illumination

Processed JSON Filename

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