A Columnbased Processing Array For Highspeed Digital Image Processing

• doi: 10.1109/ARVLSI.1999.756036
• title: A column-based processing array for high-speed digital image processing
• publisher: IEEE
• isbn: 0-7695-0056-0
• issn: 1522-869X
• rank: 1021
• access_type: LOCKED
• content_type: Conferences
• abstract: We present a novel architecture for column-based image processing within an integrated CMOS sensor chip. The system includes a two-dimensional array of active pixel sensors, a one-dimensional array of analog-to-digital converters along one side of the sensor array, an array of static random access memory (SRAM) cells, and a one-dimensional array of parallel digital processing units. The architecture offers much potential for scalability, primarily due to a rotation of the digital bits coming out of the analog-to-digital converter. Each data converter produces an 8-bit value, which is then stored horizontally in an SRAM byte extending across 8 columns of pixels. This arrangement of data enables 8-bit parallel processing by each of the arithmetic logic units (ALUs), which also extends along 8 pixel columns. This grouping of 8 columns is referred to as a block-column. We describe the architecture and discuss implementation issues encountered during the design of two separate test devices fabricated in a 0.35 /spl mu/m digital CMOS process. We also present results of an architectural analysis with example algorithms.
• article_number: 756036
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=756036
• html_url: https://ieeexplore.ieee.org/document/756036/
• abstract_url: https://ieeexplore.ieee.org/document/756036/
• publication_title: Proceedings 20th Anniversary Conference on Advanced Research in VLSI
• conference_location: Atlanta, GA, USA
• conference_dates: 21-24 March 1999
• publication_number: 6125
• is_number: 16373
• publication_year: 1999
• publication_date: 21-24 March 1999
• start_page: 42
• end_page: 56
• citing_paper_count: 4
• citing_patent_count: 1
• download_count: 255
• insert_date: 20020806
• index_terms:
  • ieee_terms:
    • Digital images
    • Sensor arrays
    • CMOS image sensors
    • CMOS process
    • Sensor systems
    • Analog-digital conversion
    • Random access memory
    • Image processing
    • SRAM chips
    • Scalability
  • dynamic_index_terms:
    • Image Processing
    • Digital Images
    • Digital Image Processing
    • Boundary Extraction
    • Image Optimization
    • Computer Image Processing
    • High-speed Processing
    • High Processing Speed
    • Processing Unit
    • Test Device
    • Sensor Array
    • Active Sensors
    • Potential Scale
    • Digital Unit
    • Pixel Column
    • Static Random Access Memory
    • Digital Camera
    • Test System
    • Control Signal
    • Operation Process
    • Edge Detection
    • Array Size
    • Registration Status
    • State Registers
    • Enrollment Status
    • Pixel Array
    • Test Chip
    • Pixel Pitch
    • Digital Circuits
    • Digital Circuitry
    • Processing Circuit
    • Color Conversion
    • Clock Frequency
    • Storage Units
    • Processing Architecture
• isbn_formats:
  • format: Print ISBN, value: 0-7695-0056-0, isbnType: Historical
• authors:
  • Author Name: T. Morris
    Affiliation: MS CH6-438, Intel Corporation, Chandler, AZ, USA
    Author URL: https://ieeexplore.ieee.org/author/37348103200
    ID: 37348103200
    Order: 1
    Author Affiliations:
    • MS CH6-438, Intel Corporation, Chandler, AZ, USA
  • Author Name: E. Fletcher
    Affiliation: MS CH6-438, Intel Corporation, Chandler, AZ, USA
    Author URL: https://ieeexplore.ieee.org/author/37088063079
    ID: 37088063079
    Order: 2
    Author Affiliations:
    • MS CH6-438, Intel Corporation, Chandler, AZ, USA
  • Author Name: C. Afghahi
    Affiliation: MS CH6-438, Intel Corporation, Chandler, AZ, USA
    Author URL: https://ieeexplore.ieee.org/author/37088063888
    ID: 37088063888
    Order: 3
    Author Affiliations:
    • MS CH6-438, Intel Corporation, Chandler, AZ, USA
  • Author Name: S. Issa
    Affiliation: MS CH6-438, Intel Corporation, Chandler, AZ, USA
    Author URL: https://ieeexplore.ieee.org/author/37088069065
    ID: 37088069065
    Order: 4
    Author Affiliations:
    • MS CH6-438, Intel Corporation, Chandler, AZ, USA
  • Author Name: K. Connolly
    Affiliation: MS CH6-438, Intel Corporation, Chandler, AZ, USA
    Author URL: https://ieeexplore.ieee.org/author/37088068353
    ID: 37088068353
    Order: 5
    Author Affiliations:
    • MS CH6-438, Intel Corporation, Chandler, AZ, USA
  • Author Name: J.-C. Korta
    Affiliation: MS CH6-438, Intel Corporation, Chandler, AZ, USA
    Author URL: https://ieeexplore.ieee.org/author/37088067675
    ID: 37088067675
    Order: 6
    Author Affiliations:
    • MS CH6-438, Intel Corporation, Chandler, AZ, USA

Image Sensor

• sensor_type: CMOS
• resolution: 64 x 64 pixels
• dynamic_range: Not specified
• pixel_size: 10 µm
• dark_current: Not specified

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

Applications & Benefits

• cell_imaging: Used for image capture in digital cameras, video cameras, and computer vision systems.
• benefits: Advantages include higher integration potential, scalability, lower power consumption, and the ability to perform digital processing on-chip.

Supporting Organizations

• supported_by: Intel Corporation

Manuscript Details

• publication_date: 21-24 March 1999

Relevancy Score

• score: 10
• missing_fields:
  • dynamic_range
  • dark_current
  • focal_length
  • aperture
  • field_of_view
  • distortion
  • frame_rate
  • signal_to_noise_ratio
  • sensitivity
  • shutter_speed
  • power_consumption
  • noise

Processed JSON Filename

request_2e282817-447f-4515-82fc-b98bc16c35a1-a_columnbased_processing_array_for_highspeed_digital_image_processing.json