A 12Bit 25Bitphase Columnparallel Cyclic Adc

• doi: 10.1109/TVLSI.2018.2871341
• title: A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC
• publisher: IEEE
• isbn:
• issn: 1557-9999
• rank: 275
• access_type: LOCKED
• content_type: Journals
• abstract: A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/-0.5 LSB and +0.8/-0.9 LSB, respectively. The ADC consumes 435-μW of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 μm show that it is suitable for column-parallel readout in CMOS image sensors.
• article_number: 8478824
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8478824
• html_url: https://ieeexplore.ieee.org/document/8478824/
• abstract_url: https://ieeexplore.ieee.org/document/8478824/
• publication_title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• conference_location:
• conference_dates:
• publication_number: 92
• is_number: 8595476
• publication_year: 2019
• publication_date: Jan. 2019
• start_page: 248
• end_page: 252
• citing_paper_count: 16
• citing_patent_count: 0
• download_count: 1710
• insert_date: 20181002
• index_terms:
  • ieee_terms:
    • Power demand
    • CMOS image sensors
    • Capacitors
    • Signal resolution
    • Very large scale integration
    • Standards
    • CMOS technology
  • author_terms:
    • 25-bit cyclic ADC
    • CMOS image sensor (CIS)
  • dynamic_index_terms:
    • Power Consumption
    • Conversion Rate
    • Comparable Number
    • Standard CMOS
    • Monte Carlo Simulation
    • Monte Carlo Method
    • Sample Holder
    • Analog-to-digital Converter
    • Analog-to-digital
    • Digital-to-analog Converter
    • Per Cycle
    • Figure Of Merit
    • Figure-of-merit
    • Digital Signal
    • Single Stage
    • Input Range
    • Amplifier Gain
    • Subrange
    • Gain Error
    • Clock Phase
    • Clock Generator
• authors:
  • Author Name: Amandeep Kaur
    Affiliation: Electrical Engineering Department, IIT Delhi, New Delhi, India
    Author URL: https://ieeexplore.ieee.org/author/37085856535
    ID: 37085856535
    Order: 1
    Author Affiliations:
    • Electrical Engineering Department, IIT Delhi, New Delhi, India
  • Author Name: Deepak Mishra
    Affiliation: Electrical Engineering Department, IIT Delhi, New Delhi, India
    Author URL: https://ieeexplore.ieee.org/author/37085433827
    ID: 37085433827
    Order: 2
    Author Affiliations:
    • Electrical Engineering Department, IIT Delhi, New Delhi, India
  • Author Name: Mukul Sarkar
    Affiliation: Electrical Engineering Department, IIT Delhi, New Delhi, India
    Author URL: https://ieeexplore.ieee.org/author/37394227700
    ID: 37394227700
    Order: 3
    Author Affiliations:
    • Electrical Engineering Department, IIT Delhi, New Delhi, India

Image Sensor

• sensor_type: CMOS
• resolution: 12-bit
• dynamic_range: Not explicitly mentioned
• pixel_size: 5.6 μm
• dark_current: Not explicitly provided

Optical Data

• focal_length: Not explicitly provided
• aperture: Not explicitly provided
• field_of_view: Not explicitly provided
• distortion: Not explicitly provided

Performance Metrics

• frame_rate: 1600 fps for a 1-Mpixel array
• signal_to_noise_ratio: 63.15 dB
• sensitivity: Not explicitly provided
• shutter_speed: Not explicitly provided
• power_consumption: 435 μW effective power (0.8 mW total including circuitry)
• noise: Not explicitly provided

Applications & Benefits

• cell_imaging: The designed ADC will result in a frame-rate of greater than 1600 frames/s for a 1-Mpixel array.
• benefits: Low power consumption, high-speed readout, improved conversion rate in high-resolution CMOS image sensors.

Supporting Organizations

• supported_by: IIT Delhi, UMC 180-nm CMOS technology

Manuscript Details

• publication_date: Jan. 2019

Relevancy Score

• score: 10
• missing_fields:
  • fill factor
  • quantum efficiency
  • readout speed
  • noise sources
  • microlenses
  • on-chip colour filters
  • global or rolling shutters
  • backside illumination

Processed JSON Filename

request_e0a29c2f-2182-4c63-8be5-e9489e2bb61c-a_12bit_25bitphase_columnparallel_cyclic_adc.json