A 1000 Fps Vision Chip Based On A Dynamically Reconfigurable Hybrid Architecture Comprising A Pe Array Processor And Selforganizing Map Neural Network

• doi: 10.1109/JSSC.2014.2332134
• title: A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network
• publisher: IEEE
• isbn:
• issn: 1558-173X
• rank: 259
• access_type: LOCKED
• content_type: Journals
• abstract: This paper proposes a vision chip hybrid architecture with dynamically reconfigurable processing element (PE) array processor and self-organizing map (SOM) neural network. It integrates a high speed CMOS image sensor, three von Neumann-type processors, and a non-von Neumann-type bio-inspired SOM neural network. The processors consist of a pixel-parallel PE array processor with $O(N\times N)$ parallelism, a row-parallel row-processor (RP) array processor with $O(N)$ parallelism and a thread-parallel dual-core microprocessor unit (MPU) with $O(2)$ parallelism. They execute low-, mid- and high-level image processing, respectively. The SOM network speeds up high-level processing in pattern recognition tasks by $O(N/4\times N/4)$, which improves the chip performance remarkably. The SOM network can be dynamically reconfigured from the PE array to largely save chip area. A prototype chip with a 256$\,\times\,$256 image sensor, a reconfigurable 64$\,\times\,$ 64 PE array processor/16$\,\times\,$ 16 SOM network, a 64$\,\times\,$ 1 RP array processor and a dual-core 32-bit MPU was implemented in a 0.18 $\mu$m CMOS image sensor process. The chip can perform image capture and various-level image processing at a high speed and in flexible fashion. Various complicated applications including M-S functional solution, horizon estimation, hand gesture recognition, face recognition are demonstrated at high speed from several hundreds to ${>}$ 1000 fps.
• article_number: 6853420
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853420
• html_url: https://ieeexplore.ieee.org/document/6853420/
• abstract_url: https://ieeexplore.ieee.org/document/6853420/
• publication_title: IEEE Journal of Solid-State Circuits
• conference_location:
• conference_dates:
• publication_number: 4
• is_number: 6881756
• publication_year: 2014
• publication_date: Sept. 2014
• start_page: 2067
• end_page: 2082
• citing_paper_count: 79
• citing_patent_count: 0
• download_count: 2794
• insert_date: 20140711
• index_terms:
  • ieee_terms:
    • Arrays
    • Biological neural networks
    • Neurons
    • Image processing
    • Pattern recognition
    • Image sensors
    • Registers
  • author_terms:
    • Dynamic reconfiguration
    • hybrid architecture
    • multiple levels of parallelism
    • pattern recognition
    • processing element (PE)
    • SOM neural network
    • vision chip
  • dynamic_index_terms:
    • Neural Network
    • Self-organizing Map
    • Kohonen
    • Function Neural Network
    • Hybrid Architecture
    • Vector Process
    • Vector Facility
    • Array Processor
    • Dynamic Reconfiguration
    • Reconfigurable Architecture
    • Processing Element Array
    • Self-organizing Map Neural Network
    • Vision Chips
    • Image Processing
    • High Speed
    • Recognition Task
    • Face Recognition
    • Image Sensor
    • Camera Sensor
    • Image Capture
    • High-level Processing
    • Higher-level Processes
    • Higher-level Cognitive Processes
    • High-level Cognitive Processes
    • Hand Gestures
    • Gesture Recognition
    • Chip Area
    • Pixel Array
    • Binary Image
    • Low-level Processing
    • Lower-level Processes
    • Readout Circuit
    • Face Detection
    • Human Faces
    • Complicated Algorithms
    • Processing Speed
    • Psychomotor Speed
    • Clock Cycles
    • System Performance
• authors:
  • Author Name: Cong Shi
    Affiliation: Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37086359587
    ID: 37086359587
    Order: 1
    Author Affiliations:
    • Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
  • Author Name: Jie Yang
    Affiliation: Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37089545294
    ID: 37089545294
    Order: 2
    Author Affiliations:
    • Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
  • Author Name: Ye Han
    Affiliation: Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37086634093
    ID: 37086634093
    Order: 3
    Author Affiliations:
    • Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
  • Author Name: Zhongxiang Cao
    Affiliation: Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37086636459
    ID: 37086636459
    Order: 4
    Author Affiliations:
    • Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
  • Author Name: Qi Qin
    Affiliation: Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37086636609
    ID: 37086636609
    Order: 5
    Author Affiliations:
    • Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
  • Author Name: Liyuan Liu
    Affiliation: Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37085745851
    ID: 37085745851
    Order: 6
    Author Affiliations:
    • Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
  • Author Name: Nan-Jian Wu
    Affiliation: Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37286754000
    ID: 37286754000
    Order: 7
    Author Affiliations:
    • Chinese Academy of Sciences, Institute of Semiconductors, Haidian District, Beijing, China
  • Author Name: Zhihua Wang
    Affiliation: Department of Electronic Engineering, Tsinghua University, Haidian District, Beijing, China
    Author URL: https://ieeexplore.ieee.org/author/37279252700
    ID: 37279252700
    Order: 8
    Author Affiliations:
    • Department of Electronic Engineering, Tsinghua University, Haidian District, Beijing, China

Image Sensor

• sensor_type: CMOS
• resolution: 256x256 pixels
• dynamic_range: Not specified
• pixel_size: Not specified
• dark_current: Not specified

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

• frame_rate: 1000 fps (can perform image capture at 2000 fps)
• power_consumption: 630 mW at 1000 fps

Applications & Benefits

• cell_imaging: Used in hand gesture recognition, face detection and recognition, horizon estimation, and various image processing applications.
• benefits: High speed (1000 fps) image capture and processing, flexible for complicated vision applications.

Supporting Organizations

• supported_by: National Natural Science Foundation of China, Special Funds for Major State Basic Research Project of China

Manuscript Details

• publication_date: Sept. 2014

Relevancy Score

• score: 9
• missing_fields:
  • dynamic_range
  • pixel_size
  • dark_current
  • noise
  • optical_data

Processed JSON Filename

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