11Bit Columnparallel Singleslope Adc With Firststep Halfreference Ramping Scheme For Highspeed Cmos Image Sensors

• doi: 10.1109/JSSC.2021.3059909
• title: 11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors
• publisher: IEEE
• isbn:
• issn: 1558-173X
• rank: 17
• access_type: LOCKED
• content_type: Journals
• abstract: A first-step half-reference ramping (FHR) readout scheme is presented in this study for high frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the conversion speed of a single-slope (SS) analog-to-digital converter (ADC) by applying a binary-weighted searching algorithm at the first A/D conversion attempt. By effectively reducing the reference signal range, the proposed FHR readout scheme can reduce the number of A/D conversion steps in the SS ADC while maintaining the ADC performance. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed FHR scheme becomes more effective as the bit-depth of the ADC increases. A prototype CIS with a column-parallel 11-bit SS ADC was fabricated in a 0.11-μm 1P4M CIS process with a 2.9-μm pixel pitch. A maximum frame rate of 570 frames/s was achieved with a 1024×240 pixel resolution, corresponding to a 140.08 Mp/s pixel rate. Total power consumption was 57.2 mW under 2.8 V for pixel readout and 1.8 V for readout circuitry. When compared with the conventional 11-bit SS ADC, the proposed FHR scheme shortens the total A/D conversion time by 38.4%. The prototype CIS demonstrated the figure of merits (FoM) of 0.84 e-·nJ and 0.41 e-·nJ/step.
• article_number: 9366299
• pdf_url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9366299
• html_url: https://ieeexplore.ieee.org/document/9366299/
• abstract_url: https://ieeexplore.ieee.org/document/9366299/
• publication_title: IEEE Journal of Solid-State Circuits
• conference_location:
• conference_dates:
• publication_number: 4
• is_number: 9466892
• publication_year: 2021
• publication_date: July 2021
• start_page: 2132
• end_page: 2141
• citing_paper_count: 49
• citing_patent_count: 0
• download_count: 4758
• insert_date: 20210301
• index_terms:
  • ieee_terms:
    • Analog-digital conversion
    • Generators
    • Random access memory
    • Prototypes
    • Capacitors
    • Voltage control
    • Timing
  • author_terms:
    • CMOS image sensor (CIS)
    • column-parallel readout
    • first-step half-reference ramping (FHR) readout scheme
    • high-speed single-slope (SS) analog-to-digital converter
  • dynamic_index_terms:
    • Single-slope Analog-to-digital Converter
    • Single Slope Analog-to-digital Converters
    • Figure Of Merit
    • Figure-of-merit
    • Reference Signal
    • Conversion Time
    • High Frame Rate
    • Conversion Step
    • Total Power Consumption
    • Pixel Pitch
    • Single Slope
    • Readout Scheme
    • Readout Strategy
    • Image Quality
    • Dark Conditions
    • Voltage Levels
    • Lower Section
    • Noise Suppression
    • Active Noise Control
    • Noise-canceling
    • Noise Cancellation
    • Control Logic
    • Conventional Scheme
    • Upper Section
    • Least Significant Bit
    • Low Bit
    • Most Significant Bit
    • High Bit
    • Highest Bit
    • Conventional Architecture
    • Horizontal Stripes
    • Output Pixel
    • Digital Domain
    • Offset Error
    • Clock Period
    • Clock Periods
    • Adjacent Columns
    • Result Of Conversion
    • Converse Result
    • Digital Code
    • Additional Switching
• authors:
  • Author Name: Hyeon-June Kim
    Affiliation: Department of Electrical Information Communication Engineering, Kangwon National University, Samcheock, South Korea
    Author URL: https://ieeexplore.ieee.org/author/37085397854
    ID: 37085397854
    Order: 1
    Author Affiliations:
    • Department of Electrical Information Communication Engineering, Kangwon National University, Samcheock, South Korea

Image Sensor

• sensor_type: CMOS
• resolution: 1024x240
• dynamic_range: 73.6 dB
• pixel_size: 2.9 µm
• dark_current: 168 μV rms / 2.05 e− rms

Optical Data

• focal_length: Not specified
• aperture: Not specified
• field_of_view: Not specified
• distortion: Not specified

Performance Metrics

• frame_rate: 570 fps
• power_consumption: 57.2 mW
• noise: 0.23 LSB rms, 88.56 μV rms

Applications & Benefits

• cell_imaging: High-speed CMOS image sensor suitable for various applications including smartphones and medical devices.
• benefits: High frame rate, low power consumption, reduced A/D conversion time.

Supporting Organizations

• supported_by: Kangwon National University, National Research Foundation of Korea (NRF)

Manuscript Details

• publication_date: July 2021

Relevancy Score

• score: 10

Processed JSON Filename

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